Results 1 ... 250 found in all logged channels for 'f:asc fpga' | →
(pest) gregorynyssa[asciilifeform]: So the bottleneck of the realization of Loper OS lies in having an FPGA of reasonable density which is also completely transparent in its design.
(pest) bitbot[asciilifeform]: Logged on 2024-06-22 23:23:02 gregorynyssa[billymg]: asciilifeform: Have you done any more reverse-engineering of FPGAs over the past year?
(pest) gregorynyssa[asciilifeform]: asciilifeform: Have you done any more reverse-engineering of FPGAs over the past year?
(pest) asciilifeform remembers -- tho can't find thread in o(1) presently -- an episode where asciilifeform , thoroughly tired of that nonsense, went to draw up a board on which 'let's put 1G of fast sram + fpga and be done with it', only to discover that nobody's making standalone srams that could keep up with reasonable fpga clock, a
(pest) bitbot[asciilifeform]: Logged on 2024-03-01 20:15:04 phf[jonsykkel]: 􏿽so if the goal is to replicate the scheme cpu path, the output must be something like an input for a foundry. if otherwise you're going to run it on fpga, then it's trivial to construct a scheme "core" yourself of similar complexity to scheme cpu from first principles, beca
(pest) asciilifeform: fpga was orig. meant for slow-prototyping of vlsi. ended up used in released products rather by happenstance, as vlsi fab cost 'went to moon'
(pest) bitbot[asciilifeform]: Logged on 2023-02-12 12:40:30 asciilifeform[jonsykkel|deedbot|awt]: ( for that matter, historically in fpga marketing lit 'moar gates' has usually meant 'in the form of proprietary on-die appliances' rather than 'bigger sea o'gates' fwiw )
(pest) asciilifeform: http://logs.bitdash.io/pest/2024-03-01#1032472 << vlsi is in some ways ~easier~ than fpgaism (not need to sew the thing to fit a particular pile of on-die gadgets -- and the routing fabric b/w them -- just-so)
(pest) asciilifeform not looked at the fpga cadr in a while, wonders what chip/board-specific pheatures it makes use of
(pest) bitbot[asciilifeform]: (trilema) 2018-01-17 asciilifeform: some people spent $10k's on their collections of bolixiana. and imagine that these will become worthless if an accurate fpgalogical emulator appears. and for all i know , this is true. i simply don't care.
(pest) asciilifeform: crtdaydreams: wainot go and write? afaik there aint any kinda lisp fpga synth at all atm
(pest) asciilifeform: the 'writing in the sand on the beach' aspect of this (where fpga regularly 'obsoleted' and re-editioned) is likely why we still dunhave (and aint about to) a serious open synth tool
(pest) crtdaydreams[asciilifeform]: I'm thinking as versatile as a rpi, but instead of an arm chip, you've got an FPGA
(pest) asciilifeform: the fpga vendors dun ~want~ anybody to have a usefully-large, 100% doc'd fpga.
(pest) crtdaydreams[asciilifeform]: its cheaper and less risky to de-lid an off-the-shelf fpga chip rather than your precious ivorys
(pest) asciilifeform: point was that the netlist generator / optimizer part is by far the easiest, stood next to the 'fully reverse a recent fpga and then whatever successors' part
(pest) crtdaydreams[asciilifeform]: Well it might be dirty, but having a translation layer for an FPGA arch like the ecp-5?
(pest) asciilifeform still curious what annoying thing folx expect a boobytrapped fpga synth toolchain to do, aside from uploading yer src to pastebin for public to laff at or perhaps formatting yer hdd
(pest) asciilifeform: e.g. 'sea of gates' fpga plenty big enuff to hold a nic phy + pestron has been avail. for 5+ yrs nao
(pest) crtdaydreams[asciilifeform]: the basic architecture for what I propose is really not much different from an fpga anyway
(pest) crtdaydreams[asciilifeform]: http://logs.nosuchlabs.com/log/pest/2023-09-27#1031081 << every structure ought to be mutable from the level of hardware. think of a metacircular fpga. you should be allowed to write (in realtime-cpu cycles) a cpu module for e.g. hardware-accelerated serpent and be able to integrate that into any level of execution during
(pest) asciilifeform: http://logs.bitdash.io/pest/2023-09-27#1030503 << comment wasn't re radio , but a later thrd re fpga implementation of correct pestron complete w/ nic
(pest) crtdaydreams[asciilifeform]: are you talking about i.e. deadmans switch to wipe memory and flash over fpga?
(pest) asciilifeform: ( or even fpga )
(pest) asciilifeform: http://logs.bitdash.io/pest/2023-05-15#1026131 << asciilifeform has a working py3 (for fpgaism) but iirc it is absent on standard dulap gentoo
(pest) asciilifeform: see e.g. thread re economics of fpga biz, re wai erry vendor to date ended up selling ~same ~indigestible thing
(pest) asciilifeform: ( for that matter, historically in fpga marketing lit 'moar gates' has usually meant 'in the form of proprietary on-die appliances' rather than 'bigger sea o'gates' fwiw )
(pest) bitbot[cgra|asciilifeform]: Logged on 2023-02-02 10:13:12 asciilifeform[4]: will note tho that he did not have notion of stuffing lubyism decoder per se into fpga; rather, to use the latter as a pass-through packet filter, with regular comp receiving valid packets strictly
(pest) asciilifeform will note tho that he did not have notion of stuffing lubyism decoder per se into fpga; rather, to use the latter as a pass-through packet filter, with regular comp receiving valid packets strictly
(pest) signpost[asciilifeform]: yeah, I bought that fpga item with nic you mentioned a while back
(pest) asciilifeform: throwing speaker/nethash/chainhash outta binary packets was a concession to bw conservation (these, presumably, nao would need separate logic path on fpga...)
(pest) asciilifeform: cgra: there's anuther (entirely aside from above) 'seekrit' explanation -- asciilifeform was attempting to design pest proto for, among other things, clean fpgaization
(pest) asciilifeform is gonna need x11 proto for fpga lispmisms, come to think of it, the super-ice40 board dun have a display connector...
(pest) bitbot[asciilifeform]: Logged on 2022-11-02 23:07:03 crtdaydreams[jonsykkel|awt|signpost]: http://logs.bitdash.io/pest/2022-11-02#1015379 << dun make sense, site itself still links to fpga stuff and shithub links to site
(pest) bitbot[busybot|asciilifeform]: Logged on 2022-11-02 23:07:03 crtdaydreams[jonsykkel|awt|signpost]: http://logs.bitdash.io/pest/2022-11-02#1015379 << dun make sense, site itself still links to fpga stuff and shithub links to site
(pest) asciilifeform: crtdaydreams: if you think about it, there aint a meaningful attack vector against fpga proggy ( author of boobytrap has nfi what you intend to put and where )
(pest) crtdaydreams[asciilifeform|busybot]: http://logs.bitdash.io/pest/2022-11-02#1015379 << dun make sense, site itself still links to fpga stuff and shithub links to site
(pest) asciilifeform wunders how sumbody goes from 'let's painfully reverse & map out fpga and write verilog synth' to this, but not comes up with any hypothesis other than phf's
(pest) bitbot[asciilifeform|busybot]: Logged on 2022-11-02 16:19:18 signpost: subj of FPGAs, my two arrived.
(pest) signpost[asciilifeform]: subj of FPGAs, my two arrived.
(pest) asciilifeform: the iron for e.g. lispm on fpga costs coupla hundy. but who has time, to recreate the os etc. (other than aristocrats, very busy with quite other biz, lol )
(pest) asciilifeform erry time thinks to gripe re 'fpga too small' -- recalls above photo
(pest) phf[asciilifeform]: i suspect the correct method to do an ivory-on-fpga is not to write a microcode evaluator by attempting to reconstruct netlists etc, but to write a compiler from microcode source to spit out verilog
(pest) asciilifeform back in '19 drew up a test jig pcb for 'ivory', usb <-> fpga <-> 5v buffer <-> zif socket, but not had it baked
(pest) asciilifeform: at this rate, race not b/w turtle and achilles, but 2 turtles, possib. even asciilifeform gets microscopist and working fpga netlist before the emulator folx gather the summed balls to post working emulator, lol
(pest) asciilifeform: sorta wai asciilifeform was over9000x moar interested in reviving the iron per se in modern (fpga) variant, than in emulator. i.e. the appeal from asciilifeform's pov is concretely to ~lose x86~ and its pile of undoc'd gpus etc driven mandatorily w/ c liquishit, the bookcase fulla pile of realmode->protmode->longmode hacko
(pest) asciilifeform at one time offered to dks 'let's make fpga subst for macivory' but, unsurprisingly, he had no reason to trust 'farther than could throw' so no, not paid
(pest) asciilifeform had comparatively modest objective of 'replicate macivory in fpga', notionally ~then~ at leisure archaeologize therein
(pest) asciilifeform recs to folx to get to the 'blink led at 1hz' stage before ponying up for fat fpga boards
(pest) crtdaydreams[asciilifeform|busybot]: Likely ULX3S will arrive before Icebreaker and TinyFPGA ordered in May
(pest) asciilifeform: the board in question, ftr. ( asciilifeform picked up , not tried just yet tho )
(pest) crtdaydreams[asciilifeform]: would like to bring up hypothetical hardware excursions once again, something that's been on my mind as of late is shortwave, is the idea to strap an antennae to an FPGA (with some DSP
(asciilifeform) asciilifeform: crtdaydreams: atm there aint a suitably large homogeneous fpga
(asciilifeform) asciilifeform: crtdaydreams: prolly not 'every' and 'between all component', fpga fabric is expensive delaywise
(asciilifeform) asciilifeform: crtdaydreams: they sell one (with the 100% closed-bitstream fpga they got from swallowing altera) , naturally w/ ME , how else
(asciilifeform) asciilifeform: diff is that is actually possible, hypothetically, to bake fpga into cpu (intel even made noises about offering one, tho naturally 100% closed shitware) ; then when someone devises a new instr for $op, ~all~ the irons could use it
(asciilifeform) asciilifeform: for instance, asciilifeform was expecting verisimilitude to say e.g. 'if the cpu vendors simply shipped fpga core that runs at main clock speed, wouldn't need magick instructions'
(asciilifeform) asciilifeform: iirc the fpga turd is actually reflashable, w/ the toolkit in principle could load own
(asciilifeform) asciilifeform: phf: ha, i've a 'riscv' thing from apparently same vendor that loox physically identical. but unsurprise given that they're actually chinese fpga (altera clone, sadly 100% closed toolchain) demo boards
(asciilifeform) asciilifeform: ~may~ be doable in tight asm on apu1 (w/out fpgaism) running absolutely nuffin else, w/ entire 'kernel' fitting in l0 cache.
(asciilifeform) asciilifeform: well if you've fpga, it's 'phree', at least in so far as the iron goes
(asciilifeform) asciilifeform: ideally would fpga instead of apu1's cpu, do the sha384 thing 'in iron', easily gb/s eating/shitting
(asciilifeform) asciilifeform: the 'non-annoying approach to concurrency' is to implement entire machine as fpga fabric, and let independent processes actually run on physically independent circuits. but most of what people do w/ computer in practice doesn't require any serious degree of concurrency.
(asciilifeform) asciilifeform: massively gnarly arch, btw, still boggles mind that anyone salivates to it on fpga
(pest) asciilifeform: (concretely referring to 'not just nic, but can offload packet munging from cpu to this-here fpga' items)
(asciilifeform) asciilifeform: interestingly, would be relatively simple (and 100% compat. with even the most 'evil' current x86 box) to keep it on 'option rom' of a pcie card. but afaik no one manufacturs such a card (ideally would have simply a hole for usb drive, to serve as the rom, and fpga to talk to the bus. update of kernel strictly by physically pulling the stick and writing to same)
(asciilifeform) asciilifeform: gregory5: re '90s fpgas -- see also.
(asciilifeform) asciilifeform: afaik to this day the only open-spec fpga with even close to serious gate count remains lattice's ice40.
(asciilifeform) asciilifeform: PeterL: if pestism catches on, will be very easy to bake a fpga prefilter, much cheaper (and lower mains current usage) than a beefy x86
(asciilifeform) asciilifeform: i also specifically like the idea of a non-numbertheoretical basis for the signatures -- will make it considerably easier to implement in fpga for baking dedicated (hardware) line-rate prefilters.
(asciilifeform) asciilifeform: bonechewer: if you're looking for a (slow) usb stack for fpga, actually exists, i tested on ice40
(asciilifeform) asciilifeform: the ideal usecase for fpga is to turn $device into a non-vonneumann item which doesn't need software or an os at all and still does $job.
(asciilifeform) asciilifeform: bonechewer: there nuffin magic about making a comp outta fpga -- if you use your $1000 xilinx to emulate a pentium and run poetteringware on it, you get compromised in exactly same way as a derp who bought a 'dell'
(asciilifeform) asciilifeform: bonechewer: moar or less impossible to do ~anything w/ a large (i.e. fpga, rather than cpld) xilinx w/out the onchip blobs
(asciilifeform) asciilifeform: i.e. even adequately reversed xilinx turd aint a substitute for the missing 'soup of LUTs' large homogeneous fpga.
(asciilifeform) asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2021-06-10#1038526 << ice40 has moar LUTs than any '80s fpga. and documented. i suspect you meant to ask '1980s FPGAs with the LUT count of high-end xilinx from 2021'
(asciilifeform) asciilifeform: verisimilitude: i'd much like a FPGA where each LUT has a pixel output. but not expecting such a thing to be made (even if moore's law were not dead)
(asciilifeform) asciilifeform: there's a cycle-accurate c64 and even amiga on fpga. and imho not merely from nostalgia: these boxes were actually ~fun~ to program for. because ~not~ included five bookcase's worth of changes-every-6months shitlibs
(asciilifeform) asciilifeform: trinque: unrelatedly, aiming to return to ffaism soonish. (and -- then to port to the suddenly appeared, after asciilifeform waited for decade+ -- 45,000 LUT open fpga board.
(asciilifeform) asciilifeform: Aerthean: which fpga are you using ?
(asciilifeform) asciilifeform: verisimilitude: the fpga in fg was used strictly 'as modem'. see also.
(asciilifeform) asciilifeform: and indeed much of the accumulated knowledge re comp design from vonneumann world, is inapplicable in this scenario. in fact is large part of why you can't buy a 'kilogram of fpga' as general-purpose pc.
(asciilifeform) asciilifeform: verisimilitude: i rec to get familiar w/ basics of fpgaism. simply so can see what example looks like of 'fabric' where almost nothing about e.g. memory is apriori forced on the designer (you can pick what length/width of memory to use in a particular 'island')
(asciilifeform) asciilifeform: the most accessible example of non-vm comp is fpga fabric.
(asciilifeform) asciilifeform: verisimilitude: fwiw it aint esp. hard to 'competitive w/ new intel' on fpga if correctly chosen benchmark (the most well-known example is prolly btc mining, i.e. sha2 brute)
(asciilifeform) asciilifeform: which sifive item ? iirc they make a (virtually undocumented) small fpga; and a riscv microcontroller
(asciilifeform) asciilifeform: qonfluent: actually, the ~only~ si i'd consider making, is a large homogeneous fpga . but afaik it is ~impossible to actually finance such a project , unless yer already rockefeller.
(asciilifeform) asciilifeform: qonfluent: sadly, very similar biz model in fpga world.
(asciilifeform) asciilifeform: ftr also there can be no question of a 500nm fpga holding anyffin like a nontrivial cpu. ( for comparison, e.g. ice40 -- which is ~barely~ cpu-capable -- is a 40nm product. )
(asciilifeform) asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2020-08-22#1020093 << a fpga was originally ('80s) precisely 'bag of LUTs.' the 'let's include 9000 undocumented periphs and license out the closed turds to drive'em' biz model came in '90s.
(asciilifeform) asciilifeform: there is presently no 100%-documented homogeneous fpga on market. and, for fundamental reasons, aint likely to be, 100% of fpga vendors live from the 'rent out the right to use our built-in NIC' and similar scamola
(asciilifeform) asciilifeform: ftr what asciilifeform was interested in fabbing, was simply a homogeneous-fabric fpga, scaled-up version of e.g. classic ice40 .
(asciilifeform) asciilifeform: the weakness of fpga is that the flipflops etc. cannot ~physically~ move & rearrange to the desired circuit. so they continue to take up sq. metrage, eat current, and delay signals, even after you've decided what circuit you want outta'em.
(asciilifeform) asciilifeform: fpga can be said to be 'degenerate case' of horiz. microcode -- where there is large circuit, and ~only 1~ instruction, that executes on power-up.
(asciilifeform) asciilifeform: verisimilitude: at the risk of making guess , sounds rather like fpga
(asciilifeform) asciilifeform: rather like the way fpga config worx
(asciilifeform) asciilifeform: they're obviously useful, but ~very~ expensive , for instance a 32x32 multiplier doesn't even fit in any 'ice'-series fpga
(asciilifeform) asciilifeform: sadly there aint much use for a ~40MHz mips , afaik. which is all i can get in e.g. 'ice40' fpga
(asciilifeform) asciilifeform: my interest in mips was 100% on acct of simplicity of the arch -- it fits in smallish fpga .
(asciilifeform) asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2020-05-26#1013272 << if you (or other reader) know of someone who sells fpga on muller gate , with 100% documented internals, do say. otherwise what's the complaint about ?
(asciilifeform) asciilifeform: i, for instance, mined at one pt a coin on a fpga. (before there were commercial systems for it on market, simply so happend that i was working w/ fpgas for other reasons)
(asciilifeform) asciilifeform: for e.g. rocket vanes, need within mSec . for pu pit implosion detonator, within 100nsec. (hey it worked in '40s, they had no fpga..)
(asciilifeform) asciilifeform: this btw is another + of fpgaism. can simulate 'to nanosecond'. for afaik 0 micro is this avail. (tho some vendors offer turdware for $$$)
(asciilifeform) asciilifeform: there's ~0 concept of 'debug' tho, in fpgaism. you can simulate, or prod the chip w/ oscope, but very little in between
(asciilifeform) asciilifeform: i've made 0 chip, but have fpgaisms on desk right nao w/ 0 winblowz in the loop anywhere.
(asciilifeform) asciilifeform: most folx take micro over fpga, even when it dun make logical sense
(asciilifeform) asciilifeform: ( i couldn't find fpga that'd hold a 4096b barrel shifter for any amt of money )
(asciilifeform) asciilifeform: whether you can get away w/ fpgaism depends intimately on what yer thing needs to do to those N bits to make those M
(asciilifeform) asciilifeform: for 'box takes N bits, gives M other bits, in S millisec, in 30loc' it's straight to fpga.
(asciilifeform) asciilifeform: there's an obv upside to fpga
(asciilifeform) asciilifeform: ben_vulpes: if that -- than straight to fpga.
(asciilifeform) asciilifeform: whereas mips fits in e.g. 'ice40' fpga & leaves room.
(asciilifeform) asciilifeform: fwiw asciilifeform's most 'hard real time' piece was FG. and there i cut out the von neumann machine entirely and went w/ fpga.
(asciilifeform) asciilifeform: ( and in fact the only properly kosher, i.e. wholly reversed, fpga on the market , is afaik still 'ice40' , which is rather small . just barely holds a useful mipslike w/ 64bit regs. )
(asciilifeform) asciilifeform: ideally would have simply a mipslike with ultrawide alu (which would obsolete good 80% of ffa by weight) but no existing fpga is large enuff to house this.
(asciilifeform) asciilifeform: amberglint: the huang fella is a вредитель , likely sponsored directly by the enemy. consider: with what it cost to bake his shitware to date, one could easily order a properly-open fpga made from 0. but instead he pushes xilinx's.
(asciilifeform) asciilifeform presently suspects that 'scalpl' was adlai's version of asciilifeform's 2011 'write fpga miner'. i.e. smaller roi than picking up pennies on train station.
(asciilifeform) asciilifeform: the 'igloo' fpga, as far as i could tell, was used simply to run the jtag state machine at reasonable speed (instead of 'bit bang' via the uc).
(asciilifeform) asciilifeform: fromloper1121: to add some detail from my ancient notes : the upgrade binary (i single-stepped the whole process via the jtag pins when i was curing the thing) gets loaded into the uc ram, and executes; then a packed copy of fw is flashed in, and packed copy of fpga bitstream ditto.
(asciilifeform) asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2019-12-21#1004080 << it's 100% of the fw. the extra space is fpga bitstream, there's an 'actel igloo' in there, and it gets flashed during the main fw upgrade from a turd in the latter. ( plus a header. read the sage_pill src if yer interested in the layout. )
(asciilifeform) asciilifeform: theoretically the fpga will need reflash some time around 2050. but errything else ~eternal so long as not overvoltaged.
(trilema) asciilifeform: lobbes: i mined (yes) 1st, on the pile of junkyard fpga i happened to have surrounded self with at the time .
(asciilifeform) asciilifeform: i'd happily buy a lappy that consists of ips lcd + ice40 fpga + some dram sockets. but, of course, no one makes.
(trilema) asciilifeform: the arch illustrated by the sim is simple enuff that one could fit it in, e.g., even very modest fpga. which means that nao we have reproducible kernel, gcc, toolchain, etc. for machine that can be baked , if needed, on demand, in whatever qty.
(trilema) asciilifeform: ... in 2010-11, i mined just short of single coin , on junkyard-salvaged fpgas ! until then, had none at all
(trilema) asciilifeform: it'll need, i expect, fpga + usb3 chip (cuz 200MB/sec to properly sample all the pins)
(trilema) asciilifeform: mp_en_viaje: very similar, how else. asciilifeform's observation was that even 'nvidia, but 50x slower cuz on fpga matrix, still suffices for reasonable gaming' , more like.
(trilema) asciilifeform: it's a quite large box of fpga, programmed in much same way as asciilifeform prototyped fg.
(trilema) asciilifeform: most of what's baked at e.g. tmsc, is 'verilog synthed' i.e. essentially same as fpga but w/ masked config bits.
(trilema) asciilifeform: really one only needs 2 types of ic in the box , fpga and voltage regulators...
(trilema) asciilifeform: http://btcbase.org/log/2019-04-24#1909719 << was thinking, as result of last wk's thrd, 'sane fpga could just as readily replace heathen gpu as cpu'
(trilema) asciilifeform: http://btcbase.org/log/2019-04-23#1909541 << the published sores aint especially interesting, aside from archaeological pov ( if you have fpga -- yer product is only as clean as that fpga, and there aint any clean ones gettable ; and if there were, why wouldja want to simulate a pdp11 in it ?? )
(trilema) asciilifeform: tho i do find it interesting, that it is difficult ( unlike on von neumann cpu ) to write a fpga filling that 'worx sometimes'
(trilema) asciilifeform did , repeatedly, write, and many yrs ago nao, that the 'reverse fpga' people are solving the wrong problem -- by the time they achieve anyffin, vendor simply replaces the design and laffs
(trilema) asciilifeform: ( my current understanding, is that it would be actually ~cheaper~ to bake own homogeneous-fpga thing ... )
(trilema) asciilifeform: 2y ago asciilifeform found a ru firm that cloned altera's larger fpga. they do SAME THING
(trilema) asciilifeform: the entire biz model of fpga market as it existed since 1990 or so, is based specifically on pulling this kinda scam.
(trilema) asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'
(trilema) asciilifeform: this is why fpga design ~never runs at anywhere near the max switching rate specced by the device vendor. a good synth tool 1) tries to minimize the delays 2) gives you an accurate figure for max clock, and for propagations of individual paths ( if you have e.g. dram hanging off the thing, these are critical )
(trilema) asciilifeform: he had plan to dig into the larger fpga from same vendor, and to improve the synth engine, but apparently went nowhere.
(trilema) asciilifeform: meanwhile, apparently (last yr) in heathendom, https://archive.is/UVbUE << c. wolf , author of the ice40 open fpga toolchain , apparently barfed and 'went naggum'
(trilema) asciilifeform: i'm not even raging on acct of 'draw gedanken-fpga', it can happily live for another year without being drawn. but i had to spend fucking MONTH hand-sweating out http://www.loper-os.org/?p=2875 , and similar
(trilema) asciilifeform: to briefly revisit ~earthling~ gedanken-fpga tho : it is by no means obv. that the arity has to be 4. anyffin you can tile the 2d plane with, is a legit arity. ( and if you permit 2 or moar types of tile -- then even moar possible options. )
(trilema) asciilifeform: ^ astro puzzle : calculate the minimal propagation delay in this 'fpga'. ( just how close can one park a jupiter to another before they merge.. etc )
(trilema) asciilifeform: http://btcbase.org/log/2019-04-12#1908318 << dun confuse the gedanken-fpga lut thrd with the 'ideal alu bus' one. i.e. a 64-bit bus is a set of 64 wires ; a 64-bit ~lut~ otoh is 2^64 sram cells , a planet-sized object , and with 1 lonely flipflop , lol, somewhere inside its molten core
(trilema) asciilifeform: ( picture, 1st fella to solve the exercises, gets prize, a sample fpga, lol )
(trilema) asciilifeform: it aint as if i have a queue of folx at the door demanding clean fpga lol
(trilema) asciilifeform: most folx making fpga-like things naodays, use 6bit luts
(trilema) asciilifeform: that's it, this is whole fpga.
(trilema) asciilifeform: erry type of homogeneous fpga worx on same principle. you have cell, in the cell, a shift register. for simplest example take 17 bits. (will be clear why shortly)
(trilema) asciilifeform: rrright, hence the fpga model.
(trilema) asciilifeform: lol if could 'in kitchen' why would then bother to fpga.
(trilema) asciilifeform: unlike the idjit heterogeneous fpga sold today, this item'd be a snap to simulate.
(trilema) asciilifeform: ( before you laff -- sovok in fact did bake fpga. i have a sample. but it was mid-80s state of art, i.e. metallization-programmed )
(trilema) asciilifeform: mp_en_viaje: routing is the typical eater of sq.metrage in fpga
(trilema) asciilifeform: not wholly unrelatedly, asciilifeform's semi-automated archaeology birthed a logworthy output recently. seems like in '80s there was an outfit, 'algotronix', that xilinx bought an' killed , to bury the product in patent liquishit. had entirely homogeneous fpga , made from identical ~200-transistor cells ( with simple north-south-east-west tile interconnects, and 1 flipflop inside, configged via 16bit shift register per cell, connecte
(trilema) asciilifeform: fughetting for a moment fpga : consider ordinary transistor, or even diode. it is not physically possible to bake a 'secretly smart' transistor that does s/mp-pubkey/gavin-pubkey in hopes of being put in somebody's serial port 1 day, and for it to have same analogue characteristics as genuine diode (not even speaking of what it'd look like under microscope)
(trilema) asciilifeform: mp_en_viaje: it is entirely possible to sabotage fpga in the e.g. 'philips light bulb' sense, where it burns out after 5000 hrs. or shorts + to - erry month. or similar. these are 'physical' sabotages, and imho uninteresting because indistinguishable from simply shoddy part. the interesting hypothetical mine is a ~logical~ mine.
(trilema) asciilifeform: asciilifeform's fg test process for freshly-received boards, for instance, included an (unpublished, and won't be published any time soon) set of test circuits for the fpga , that characterized the propagation delays.
(trilema) asciilifeform: correct. so, proposing to put 64-state statemachine on each pin and look for it? and what, slip the timings so dram loses bits ? this is in the 'smoke' category, logic analyzer will find the peculiar defect, and victim buys another fpga.
(trilema) asciilifeform: OriansJ: if i'm baking e.g. dram refresher -- then quite easily (and very frustratingly, in actual practice did, it is why it is ~impossible to bake a decent dram controller from scratch using fpga that hasn't been 'solved' ice40-style )
(trilema) asciilifeform: the irons that speak these 'common patterns' -- already sabotaged decade+ ago, no need even to concern with fpga..
(trilema) asciilifeform: the puzzler concerns 'general purpose' sabotaged fpga, rather than case where you know what the victim intends to connect and what protocols etc
(trilema) asciilifeform: http://btcbase.org/log/2019-04-06#1907066 << people who demand oddball instructions, can simply write own fpga payload and go happily on own path -- what am i missing ?
(trilema) asciilifeform: http://btcbase.org/log/2019-04-05#1907037 << i recommend to read the logs re 'specificity' ( picture yourself baking a sabotaged fpga , for victim whose gate net you do not know in advance. what would you put in it ? )
(trilema) asciilifeform: ( incidentally, 'can redefine cpu instructions in boot rom for custom kompyooting' dun require fpga etc. fancy modern tech, e.g. dec alpha had it )
(trilema) asciilifeform: http://btcbase.org/log/2019-03-10#1901148 << imho the ( ~homogeneous~ variant of ) fpga is actually the correct model. i.e. you get to stitch it later into however many parallel mechanisms you happen to need on a given occasion.
(trilema) asciilifeform: http://btcbase.org/log/2019-03-10#1901142 << programmable interconnect fabric ( similar to what's sold as fpga ) . iirc i detailed this in old thrd.
(trilema) asciilifeform: if it were possible to source an antifuse fpga for the http://btcbase.org/patches/fg-genesis/tree/fg.v , thing would be trooly indestructible short of incinerator or train running over it
(trilema) asciilifeform: verisimilitude: ever fpgaize your experimental archs ?
(trilema) asciilifeform: 1 annoying aspect of 'iron ffa'-gedankenexperiment, is that none of the available fpga ( either 'ice40' series, or the evil ones ) are anywhere near big enuff to prototype with. it'd have to be simulated a la http://www.loper-os.org/?p=2593 , slowly, and then straight to silicon.
(trilema) asciilifeform: ( and no it aint in 'ent' or 'diehard' or in afaik any pc rng tester, it moar or less demands fpga )
(trilema) asciilifeform: mircea_popescu: if we live to bake the fpga router thing, will be interesting to give it a ring buffer that'll hold coupla 100MB of frames, and dump'em to flash upon any unsanctioned reboot of attached irons.
(trilema) asciilifeform: sorta whole orig thrust behind asciilifeform's archaeologies, experiments in old days, fpga room, etc
(trilema) asciilifeform: BingoBoingo: the 'export ban' list is a hilarious read. ~nothing is ever removed from it, most of the thing was written in '80s-90s, and contains such items as fpga (afaik none are made in usa or have ever been, but somehow this dun stop the clowns) , and in practice seems to be used as 'lettre de cachet' against undesirables.
(trilema) asciilifeform: which means yes, working with yet-other people who shoot from hip and have baked fpga.
(trilema) asciilifeform: phf: i'ma defo refer to the emulator when baking fpga clone, it has plenty of useful info re the instruction set
(trilema) asciilifeform: and that actel, it's a 1200 gate antifuse fpga (well, without the 'f', lol), turns out.
(trilema) asciilifeform: all of'em have inscriptions of the form DDDDDD-A/B, aside from the fpga (has just the #), and the serialnum chip (cypress, and i'ma post full output from the knife+notebook when i post whole orchestra)
(trilema) asciilifeform: turns out there's even an early fpga in'ere, approx same density as the one in FG. ( but good noose is, it handles the crapple bus)
(trilema) asciilifeform: let weitekism run in soft that bolix helpfully wrote, at fpga speed
(trilema) asciilifeform: and ~then~ ( and this is what we have, but su reversers did not ) you load the thing into a (fairly inexpensive) fpga and try functional tests.
(trilema) asciilifeform: as i see it, it's damn near proof that the shitcoin 'exchange rates' are works of fiction -- 'if this is actually sellable for bitcent/ea., where is fpga ? '
(trilema) asciilifeform: considering that even coupla watt worth of fpga outweighs coupla thou. js-eaters, in general
(trilema) asciilifeform finds it vaguely interesting that js mining is still worth the candles somewhere -- suggests that the shitcoins in question are uninteresting even to fpgaize
(trilema) asciilifeform: ( it so happens that asciilifeform knows that fpga with 2MB sram became available just as that thing was written )
(trilema) asciilifeform: tldr : heathen altcoin hash algo which supposedly 'memory hard', but then you look and it only wants 2MB ( and possibly less, with optimizations) -- evidently so that fluffypony or watshisname could use ~his~ seekrit fpga..
(trilema) asciilifeform: mircea_popescu: re 'bigendian box' -- i invested in one of them 'asic emulator' mega-fpga thingies, it so happens to come with 2 ppc cores on board, can double as bigendism test system.
(trilema) asciilifeform: ( the promisetronics with 'difficult to read with microscope, believe!11' thing is, as i gather, for the various folx in the biz of loading $circuit into fpga and selling 'as asic' , it isn't of great interest to asciilifeform in particular )
(trilema) asciilifeform: ( naturally it's the big-fpga monopolist, xilinx . but it's there. )
(trilema) asciilifeform: apropos of upstack -- last wk asciilifeform did the ~yearly dig re 'does anyone actually sell fpga big enuff to demo 8192b-arithmetizer inside, fully unrolled' and turns out that yes (as of 6mo ago)
(trilema) asciilifeform: incidentally 90% written fpgaization
(trilema) asciilifeform: i have a 'i want to find out what it loox like in algebraic form , let's fpga it'
(trilema) asciilifeform: turning up the (potential! i aint even got a proof yet) weakness of the scheduler algo, took specifically the 'let's fpgaize, i think this is solid!' approach.
(trilema) asciilifeform: i'm quite reluctant to continue with the fpgaization thing unless i can get at the former.
(trilema) asciilifeform: washington can pay for its own auto-pill fpga, if they want one tho, i dun see why to do this work for them.
(trilema) asciilifeform: hey, it didn't click in asciilifeform's head either until asciilifeform went to fpgaize it..
(trilema) asciilifeform: vhdl is prolly worth a 2nd look, tho i currently suspect that it vs verilog aint a 'ada vs c' win, simply longer text that does same thing ( the only unit of data in fpgaism is really the bit, so 'types' dun exist )
(trilema) asciilifeform: ( it is not meaningful to speak of 'bitness' of fpga per se, it's just a bag of blocks, typically 4-6bit LUTs plus some arithmetizers )
(trilema) asciilifeform: funnily enuff i dun know of a single commercial/heathendom fpga that could house something of this size.
(trilema) asciilifeform: faux-fpga-worx aint exactly the most fashionable scamolas, we're looking at obscure, vs 'sexy', frauds.
(trilema) asciilifeform: presently i have nfi whether this is physically possible, or how in particular -- could be fpga-like device where somehow the components actually ~move~ into position ; or sumthing where you can optically burn away the unused tracks through 'window' ; or some yet entirely unknown trick.
(trilema) asciilifeform: mircea_popescu: this is actually how existing ic industry worx, a good half of the 'asics' are actually 'hard copy fpga', recall the early miner derps threads.
(trilema) asciilifeform: there's no 'bitness' in fpga, it's a bag of gates, if you have enuff of them you can made n-bit addder, divider, whatever one likes
(trilema) asciilifeform: i disagree -- fpga is analogous to gutenberg's movable type; classical 'asic per design' to chinese whole-plate.
(trilema) asciilifeform: FG is baked on fpga.
(trilema) asciilifeform: for that matter current FG is baked on fpga, from evil old xilinx.
(trilema) asciilifeform: and pretty much the ideal 'nonspecificity of diddling' platform, it is quite impossible to meaningfully boobytrap fpga fabric if you don't have foreknowledge of what will go into it and precisely where.
(trilema) asciilifeform: mircea_popescu: i've outlined several items, historically. will summarize for the l0gz, in order of descending ( per asciilifeform's lights ) universality : 1) sane fpga 2) sane minimal cpu 3) 8192-bit arithmetizer ( a la ye olde weitek! but for ints ) 4) 2+3 , if somehow can be fit into 1 die 5) 1chip carrierless radio ( per thread ) 6) sane ethernet controller .
(trilema) asciilifeform: which is not so bad, quite enuff for a mips ( or even the old bolix , supposing anyone had the layout for it ) but laughably small for e.g. fpga.
(trilema) asciilifeform: ( if yer baking cpu, or fpga, or other item large enuff to make the game worth the candles )
(trilema) asciilifeform: amberglint: when i went to his house 10y ago, offered to him to make fpga-ized 'ivory' , 'pro bono', if he'd only cough up with what. answr was approx 'can't , unless my master permits, and he wouldn't'
(trilema) asciilifeform: non-vonneumann machine potentially changes this, but $farm went broke before asciilifeform was able to fill 42U cabinet with fpga..
(trilema) asciilifeform: also somewhat unusually, there's a full datashit for the thing ( i.e. could drive with fpga; and there's a chinese hdmi/dvi board for it, ~20bux )
(trilema) asciilifeform: i expect decryptions will be the principal cpu expense of running a rsatronic box. at least until the fyootoor day of fpga etc
(trilema) asciilifeform: d00d had fpga & buncha FETs for taking the outputs to the magic voltage, buck converter for generating same, painstakenly hand-placed ribbon connectors, etc
(trilema) asciilifeform: heh if we had the giant fpga..
(trilema) asciilifeform: Mocky: in the past i attempted a fpga rsa also. sadly the 'ice40' would need to be about 250x bigger, for it to be bakeable
(trilema) asciilifeform: btw if mircea_popescu or somebody else here discovers that asic ( ~actual~ asic, not metallization-fpga ) can nao be baked for a coupla coin, asciilifeform will not cry; quite opposite.
(trilema) asciilifeform: mircea_popescu: iirc 1st 'btc asic' were entirely fraudulent fpga-with-sanded-top
(trilema) asciilifeform: then again, who am i to laugh, i burned '13 on hand-built fpga miner. made grand total of 0.6 coin.
(trilema) asciilifeform: imho 'sane fpga' is closest thing to 'philosopher's stone' accessible with current tech.
(trilema) asciilifeform: usg.fpga is expensive because 'intellectual property' derpitude.
(trilema) asciilifeform: it's an egregious problem in cramped fpga.
(trilema) asciilifeform: trinque: 'competition' box routes 1G/s from 48 jacks, daisy-chains with 10GB/s snakes, compiles ip filter rules into 1mil+ gate fpga fabric. how do i bake a sucks-less without large fpga ? ( we dun have large fpga, tho we do have working tiny ones )
(trilema) asciilifeform: some of the fancier units have fpga for filtrations
(trilema) asciilifeform: ( isa was a joy to interface, dun even need fpga, 3-4 ttl chips and you're cooking )
(trilema) asciilifeform: interestingly, both tx and rx end is considerably simpler, physically, than conventional periodic radio -- you dun need oscillators, tuners, at all. aside from pulse shaper, whole thing fits in fpga.
(trilema) asciilifeform: the holy grail would be to stuff this into a fpga. however ice40 isn't even remotely bigenuff.
(trilema) asciilifeform: trinque: battlefield version of the hypothetical device would need a purpose-baked (fpga) sdr. but for experiment, could use e.g. 'hackrf' ( i have it, but hesitate to recommend it to others, it comes with a massive ball of open sores rubbish, really wants an ab initio driver , ars longa, etc )
(trilema) asciilifeform: if it wasn't clear from the turdolade earlier, i'll note for the record : their published 'loader' is not ~entirely~ unrelated to the live one; it is, i suspect, prototype, from the fpga days
(trilema) asciilifeform: ( tho ordinary fpga is moar susceptible to classical pills )
(trilema) asciilifeform: i find it interesting that google's approach to building cr50 ( 'hardcopy fpga' ) is actually ~moar~ diddleable, via this method, than if they had shipped ordinary fpga
(trilema) asciilifeform: aside from golden toilet satellite gear makers, it seems to be the fpga folks who most concern with 'single event upset' ( term of art for this item ) , as a flipped bit in fpga config , even down on earth, routinely translates into magicsmokerelease
(trilema) asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with xilinx fpgas (in varying conditions of mutilation)
(trilema) asciilifeform: mircea_popescu: if i could find a fpga that sits down pad-for-pad, it becomes a $10 problem.
(trilema) asciilifeform: douchebag: ~in~ fpga. but not an off-the-shelf one, but with LUT filling in mask rom.
(trilema) asciilifeform: the only on-chip secret that'd make a diff, is if there is an iron backdoor left in fpga
(trilema) asciilifeform: but if can put a $5 fpga in its place, it's a 15 min job.
(trilema) asciilifeform: in re cr50 -- if we find which fpga was the basis, it may be possible to craft pad-for-pad replacement for the fritz.
(trilema) asciilifeform: so this doesn't exactly narrow down what the base fpga was.
(trilema) asciilifeform: and you stuff it into a fpga with a couplae custom periphs
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