billymg[asciilifeform]: $ticker btc usd
busybot: Current BTC price in USD: $41924.97
asciilifeform: http://logs.bitdash.io/pest/2023-12-08#1031542 << fwiw +ev doesn't necessarily require appeal to 'most people'. 'most people' won't buy an electron microscope, cyclotron, or even garbage truck
bitbot[asciilifeform]: Logged on 2023-12-08 21:21:00 crtdaydreams[jonsykkel|signpost]: most people don't see any kind of tenable advantage, unlikely to even consider using rudimentary smoke signals in the best-use-case scenario of such a device
asciilifeform: http://logs.bitdash.io/pest/2023-12-08#1031544 << 0-effort privacy is a false god. if yer indoors, assume the room is bugged, news at fucking 11.
bitbot[asciilifeform]: Logged on 2023-12-08 21:25:08 crtdaydreams[jonsykkel|signpost]: she explained that after her old samsung died she got one of her parents old iphones, she's not even comfortable talking around it, she's explained that on several occasions she's spoken about stuff with other people afk only to get ads for it not even a day l
asciilifeform: whining about it does absolutely 0, guaranteed.
asciilifeform: http://logs.bitdash.io/pest/2023-12-08#1031545 << it is only interesting as a proof of concept
bitbot[asciilifeform]: Logged on 2023-12-08 21:30:18 crtdaydreams[jonsykkel|signpost]: asciilifeform: you've read and understood the docs on the SCHEME-79 chip, right?
bitbot[asciilifeform]: (trilema) 2018-01-22 asciilifeform: scheme79 was a prototype, did not even have an alu!
bitbot[asciilifeform]: (trilema) 2018-01-22 phf: scheme-79 is not "whole thing published", which is something that i said in the logs multiple times also. there's AI memoes of variying detali, but the actual toolset, something called daedalus, and the corresponding daedalus files that actually describe the chip, are nowhere to be found. also die
asciilifeform: crtdaydreams: ...and if yer outdoors, and you took the fucking bug with you in yer pocket, 'room' also bugged, noshit.
crtdaydreams[asciilifeform]: http://logs.nosuchlabs.com/log/pest/2023-12-11#1032071 << this is true, but I'd like to mention that at the time of writing this I had not read AIM-559. But it's pretty much exactly what I'd been thinking of since I first learned lisp.
dulapbot: Logged on 2023-12-11 11:23:42 asciilifeform: http://logs.bitdash.io/pest/2023-12-08#1031545 << it is only interesting as a proof of concept
dulapbot: Logged on 2023-09-27 22:04:32 crtdaydreams[asciilifeform]: http://logs.nosuchlabs.com/log/pest/2023-09-27#1031081 << every structure ought to be mutable from the level of hardware. think of a metacircular fpga. you should be allowed to write (in realtime-cpu cycles) a cpu module for e.g. hardware-accelerated serpent and be able to integrate that into any level of execution during
crtdaydreams[asciilifeform]: Is this approach to hardware development in lisp unreasonable?
asciilifeform: crtdaydreams: what approach, in particular?
asciilifeform: ( and waht diff does it make? it aint as if you'll find sumbody who will take arbitrary ic mask you've generated with yer lisp and fab it for you )
asciilifeform: afaik it not even matters any longer how much dough you've got. they won't do it
asciilifeform: will only do their in-house 'standard cells'
crtdaydreams[asciilifeform]: "an embedded language in lisp for describing layout artwork so we can procedurally define generators for generalized macro components"
asciilifeform: the physical end of this aint there anymoar (and afaik hasn't been for ~20y)
asciilifeform: it'd have to be re-created, the way e.g. musk did with his rockets
crtdaydreams[asciilifeform]: Well it might be dirty, but having a translation layer for an FPGA arch like the ecp-5?
asciilifeform: hypothetically could, but the tool would be intensely particular to the arch (and yer unlikely to get 100% of the detail reqd to make it actually useful)
asciilifeform: then some time later they make an ecp6 or watever and it's back to start
crtdaydreams[asciilifeform]: the smaller ecp-5 chip is fully Reverse engineered, so the 100% detail part is already covered, but you might be tight on space
asciilifeform: fully, incl. gate delays ? wasn't, last asciilifeform knew
crtdaydreams[asciilifeform]: might be wrong
asciilifeform: thing is that they aint an optional luxury. can't bake e.g. reliable ddr2 controller w/out knowing the gate delays and geometry of errything in that thing
crtdaydreams[asciilifeform]: right
crtdaydreams[asciilifeform]: I'd like to point out that if designed correctly more than 90% of the code would be arch independent
crtdaydreams[asciilifeform]: you want the parameters for the arch to be confined the the lowest layer, then it generates it's own netlist
asciilifeform: point was that the netlist generator / optimizer part is by far the easiest, stood next to the 'fully reverse a recent fpga and then whatever successors' part
crtdaydreams[asciilifeform]: yeah definitely, but it's not to say it's impossible
crtdaydreams[asciilifeform]: its cheaper and less risky to de-lid an off-the-shelf fpga chip rather than your precious ivorys
asciilifeform: defo not impossible, but if among your objectives is 'make it for a physical box that'll remain buyable' -- aint trivial
asciilifeform: crtdaydreams: considering that you'll need to repeat whole procedure errytime they come out with a new edition -- it's a bitch
asciilifeform: it's ~why~ they regularly phase out the old and bring in new
crtdaydreams[asciilifeform]: you're thinking of playing the cat & mouse game, wouldn't it be better to just stick with one arch for a while?
asciilifeform: the fpga vendors dun ~want~ anybody to have a usefully-large, 100% doc'd fpga.
asciilifeform: it'd directly sink their biz model.
asciilifeform: you can 'stick with 1 arch' for so long as it's in print.
crtdaydreams[asciilifeform]: right, there's no panacea
asciilifeform: all of this assumes, naturally, that aim is to make a box that's available to other folx, rather than 1 unit 'under my pillow'
asciilifeform not very interested in '1, under pillow' works
crtdaydreams[asciilifeform]: could have pillowpc or be forever chained to insane arch, I'd pick pillowpc, if nothing, it's a working PoC
crtdaydreams[asciilifeform]: (with a re-usable codebase)
asciilifeform: if you haven't solved 'can make over9000 of these, and next year too' you haven't 'unchained', what you've got is a kind of updated 'ivory'
crtdaydreams[asciilifeform]: at the very least, some miracle happens and in some way shape or form you get a production run of a few thousand ICs, you'd then be at square one, you'd have a chip but nothin' to run on it
crtdaydreams[asciilifeform]: unlike ivory, you'd have the source from the ground up
crtdaydreams[asciilifeform]: It's different from a gabriel-laddelism
asciilifeform: the 'there's nuffin to run on it' is separate problem, that can't even productively approach until you've got at least coupla hndred units floating around.
asciilifeform would suggest to start with e.g. 'macsyma'+graphics
asciilifeform: aim being 'this box is fun to play with' as a first thing
crtdaydreams[asciilifeform]: I'm thinking as versatile as a rpi, but instead of an arm chip, you've got an FPGA
crtdaydreams[asciilifeform]: toy, yes, but certainly marketable
crtdaydreams[asciilifeform]: by 'nuffin to run on it' I'm referring to not even a serial repl
crtdaydreams[asciilifeform]: there's a fair bit of groundwork that if designed correctly, should be trivially decoupled from the netlist generator/underlying arch
asciilifeform: the 'writing in the sand on the beach' aspect of this (where fpga regularly 'obsoleted' and re-editioned) is likely why we still dunhave (and aint about to) a serious open synth tool
crtdaydreams[asciilifeform]: if you get around to custom ICs, you just write a netlist generator for your own arch
asciilifeform: 'if you get around to launching own moon lander' similarly...
crtdaydreams[asciilifeform]: yeah but if you actually do get around to launching your own moon lander, it's kinda useless if you can't control it
crtdaydreams[asciilifeform]: launching your moon lander without software
asciilifeform old enuff that he lost appetite for writing fw for moon launchers 'in case one day gets to launch one'
crtdaydreams[asciilifeform]: You'd be writing for a sattelite already in orbit
asciilifeform: crtdaydreams: wainot go and write? afaik there aint any kinda lisp fpga synth at all atm
asciilifeform: flag -- into hands.
asciilifeform: atm all there is in re public synth tools is that py3 crock o'shit
crtdaydreams[asciilifeform]: that's the plan, but currently too stupid
asciilifeform: and author had his balls snipped off, and iirc lost interest
asciilifeform: there's defo a torch to pick up
crtdaydreams[asciilifeform]: working slowly on un-stupiding, if I had mentorship for actually learning how to apply lisp in an intelligent manner, it'd speed up the smartifying process by a fair chunk
asciilifeform: crtdaydreams: learn like errybody else learned, by experimenting
asciilifeform: afaik no one tuned in here had 'troo mentorship', the folx who could've given it, died of old age long ago
crtdaydreams[asciilifeform]: Do you think that it would be wiser to pick an existing standarized lisp dialect like scheme or cl to write the embedded hdl lang in?
asciilifeform: pick sumthing you can run currently, if yer proggy is properly 'fit in head', can always port it later to yer space age fyootoor lisp
crtdaydreams[asciilifeform]: True, just have some inhibitions about "why did he use pedolang" lol
crtdaydreams[asciilifeform]: are you prepared to answer lots of stupid questions?
crtdaydreams[asciilifeform]: I'll make an effort to get better at asking intelligent questions, but you have years of experience I don't. So I'm sure plenty of questions I come up with are going to seem stupid.
asciilifeform must bbl but will try to answer questions at some pt, leave'em in the logs
crtdaydreams[asciilifeform]: No qs at the moment
crtdaydreams[asciilifeform]: but down the line, expect there to be some
asciilifeform: in wholly-unrealated noose, eurisko src allegedly leaked ! we only had to wait 42 yrs...