Results 1 ... 243 found in all logged channels for 'xilinx' :
(asciilifeform) Aerthean: I've also done some development on the lower-level Zynq using Vivado, which also doesn't require a paid for license. Though I have access to a license at work for some of the bigger
Xilinx FPGAs.
(asciilifeform) Aerthean: I'm going to be doing some development on one of the beefier
Xilinx Spartan-6s that use ISE rather than Vivado
(asciilifeform) gregorynyssa: problem is, no one sells densely etched LUTs as a generic commodity. everyone (
Xilinx, Intel...) sells "solutions," or worse, "experiences," but I still see two narrow avenues out of this mess:
(asciilifeform) Aerthean: Eventually I gave up as I had other work to do, and didn't have the motivation to find and tear out all the
Xilinx'isms that prevented it from building
(asciilifeform) Aerthean: Ah, yeah I followed along with some of the musl work, I put some effort into building a musl-based FreeRTOS system for a
Xilinx Zynq
(trilema) a111: Logged on 2019-04-17 22:45 asciilifeform: i suspect that proprietor of 'gowin' et al is not thinking 'how do i vanquish the reich' but instead 'how do i chisel enuff revenue away from
xilinx to build palace in miami for my 4 sons'. and i betcha already built.
(trilema) a111: Logged on 2019-04-17 19:26 asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what
xilinx does but slightly cheaper , out of chinesium'
(trilema) mircea_popescu: not the same thing ~at all~ however. for one thing, it comes with the
xilinx shitstack. for the other, it's a sack large enough to contain a car. we're talking about the actual car.
(trilema) a111: Logged on 2018-06-14 18:51 asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with
xilinx fpgas (in varying conditions of mutilation)
(trilema) a111: Logged on 2018-01-11 16:58 a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks;
xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
(trilema) apeloyee: it's the 1 product currently sold, that's worth buying. << and the
xilinx item in 'fuckgoats'?
(trilema) a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks;
xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
(trilema) a111: Logged on 2017-09-02 19:58 asciilifeform: large
xilinx chips also have 'hard' periphs inside, e.g. multers, adders, shifters, various
(trilema) phf: right, that's the first thought when you have your cadr up. "oh wait, i need to go fuck around with
xilinx tooling to make any kind of changes here)
(trilema) a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like
xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like
xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
(trilema) a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like
xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like
xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
(trilema) a111: Logged on 2017-08-21 21:30 spyked hates
xilinx with passion. if only because of the bloated software
(trilema) spyked hates xilinx with passion. if only because of the bloated software
(trilema) mircea_popescu: you know, originally tmsr embeddable work was done on
xilinx. recently discovered superior alternative,
(trilema) a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only
xilinx's closed turd knows where they are in the routing fabric;
(trilema) a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (
xilinx, altera, lattice, a few others) have the same business model
(trilema) mod6: <+asciilifeform> even build -- himself. << one of the things im gonna be doing here, maybe with some handholding, is flashing
xilinx chip with your fg.v
(trilema) mod6: i did get that
xilinx platform cable usb deal in the mail too.
(trilema) mod6: i was thinking about taking my
xilinx board and seeing if I can throw your fg-genesis on there.
(trilema) mircea_popescu: i don't know how you can audit a
xilinx chip. but if you did, asciilifeform would definitely be interested in hearing.
(trilema) mircea_popescu: well, we don't trust
xilinx for critical infreastructure for the ~same reason we don'tr trust windows.
(trilema) mircea_popescu: so you are trusting
xilinx to actually do what it says ? and this with code that you can't audit ?
(trilema) a111: Logged on 2017-03-28 15:03 mod6: i did wanna get a few
xilinx boards to play with... but first ill see what I can learn with the other stuff I got. i also bought a soldering iron.
(trilema) mod6: i did wanna get a few
xilinx boards to play with... but first ill see what I can learn with the other stuff I got. i also bought a soldering iron.
(trilema) mircea_popescu: (lasts, not because chickens will become
xilinx fans, but because the last people who know how it works will die, and then their writings will... BE MOVED TO NEW DIRECTORIES. and that's that.)
(trilema) a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (
xilinx, altera, lattice, a few others) have the same business model
(trilema) a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only
xilinx's closed turd knows where they are in the routing fabric;
(trilema) mircea_popescu: well it's unclear what the fuck it'll be, but it's pretty evident, at least to me, that the chinese ARE trying to erode the whole
xilinx tower of ip.
(trilema) sbp: "and only
xilinx's closed turd knows where they are in the routing fabric" — ugh
(trilema) gabriel_laddel: To any "hackers" reading the logs - rather than going after hackteam, try
xilinx, lattice semiconductor next time?
(trilema) ascii_field: and you don't have the ones you might like, but solely the ones the chip came with from
xilinx etc
(trilema) ascii_field: (and only a paid-up, to the tune of 100K+ usd, or well-cracked,
xilinx toolchain, will even talk to the $200-300 ones)
(trilema) assbot: Logged on 17-06-2015 17:32:11; ascii_field: (
xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
(trilema) ascii_field: (
xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
(trilema) assbot: Logged on 17-06-2015 13:17:59; asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only
xilinx's closed turd knows where they are in the routing fabric;
(trilema) ascii_field: (before anyone spits back the old paper re: the fact of c-gates implemented on
xilinx fabric - go and see how many of them you can fit. and how much room left for interconnects.)
(trilema) ascii_field: gabriel_laddel: to avoid rehashing ancient thread for a fifth time, stuck at the realization that reversing
xilinx is futile.
(trilema) ascii_field: trinque: you're talking about reverse-engineering, a la nvidia driver,
xilinx (see old thread, etc.)
(trilema) mircea_popescu: asciilifeform: at the risk of repeating the last 100+
xilinx threads <<< basically, there was no torvalds for hardware. yet.
(trilema) mircea_popescu: asciilifeform:
xilinx ships a set of identially-functioning turdlibraries for both languages. << one wonders how they actually achieved this.
(trilema) decimation: my understanding is tha altera is generally easier to deal with here, because they actually do their own r&d to produce these 'ip cores', whereas
xilinx tends to contract it out - involving third parties in your product
(trilema) mircea_popescu: <asciilifeform> you'd have to buy '
xilinx' or 'altera' - the company - to go with the chip. and publicly gut it. << it will happen.
(trilema) assbot: debit-
xilinx bitstream decompiler project has been vanished? or does someone know the URL | Comp.Arch.FPGA | FPGARelated.com
(trilema) mircea_popescu: <asciilifeform> bounce: search channel logs re: at least three separate discussions of how this came to be << you know, giving terms like "
xilinx" is better than an empty search entreaty. he doesn't know what to search for.
(trilema) assbot: NSA Approved Defense-Grade Spartan-6Q FPGA in Production for Highest Level Cryptographic Capabilities Strengthens
Xilinx Secure Leadership - Aug 31, 2011
(trilema) pankkake: Our first larger scale immersion cooled cluster consisted of 6048
Xilinx®Spartan-6 FPGAs in 24 tanks and was built in early 2012 with the Bitcoin still below $5.
(trilema) benkay: sounds like the
xilinx tools are designed to implement a certain set of routines in silicon but the silicon itself can't change the implemented routines until you bake the configuration of the fpga into the fpga itself. am i close?
(trilema) benkay: asciilifeform: why do you need to reverse the
xilinx toolchain?
(trilema) Vbs: Ken just gave them the optimized
xilinx RTL code he optimized