Results 1 ... 250 found in all logged channels for 'xilinx' | →
(pest) asciilifeform: crtdaydreams: at one time used xilinx's (for e.g. FG) but not intending to again
(pest) asciilifeform: the alternative is fwiw the vendor's closed turd (in which case no reason not to use xilinx's, they sell 20x larger chips); or 'write own'
(asciilifeform) asciilifeform once managed to actually build & enxilinx 'opensparc'
(asciilifeform) asciilifeform: incl. xilinx's 'periph cores' and other 'well here's a cpu , but whatcha gonna do w/out sdram, nic, etc, here's ours'
(asciilifeform) asciilifeform had one w/ a xilinx where cpu normally lives
(asciilifeform) crtdaydreams: Biggest roadblock would not just be dough, but having sane FGPA fundamentals; if you were to say use Xilinx over Alterra completely diff lang to interface with, resulting in a different core for the lisp.
(asciilifeform) gregory5: The famous FPGA vendors are Xilinx, Altera, and Lattice. Among these, Xilinx is the "boss." Altera was acquired by Intel in 2015
(asciilifeform) punkman: "The open source BSD licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, and is capable of booting µClinux."
(asciilifeform) asciilifeform: bonechewer: there nuffin magic about making a comp outta fpga -- if you use your $1000 xilinx to emulate a pentium and run poetteringware on it, you get compromised in exactly same way as a derp who bought a 'dell'
(asciilifeform) asciilifeform: (on top of this, the usefully large xilinxen sell for ~weight in diamonds)
(asciilifeform) asciilifeform: bonechewer: moar or less impossible to do ~anything w/ a large (i.e. fpga, rather than cpld) xilinx w/out the onchip blobs
(asciilifeform) bonechewer: Maybe I am overconfident, but I fail to see how the adversary could compromise a device using a Xilinx FPGA as long as its designer did not use the Xilinx proprietary tools nor on-chip blobs
(asciilifeform) asciilifeform: i.e. even adequately reversed xilinx turd aint a substitute for the missing 'soup of LUTs' large homogeneous fpga.
(asciilifeform) dulapbot: (trilema) 2018-07-19 asciilifeform: mircea_popescu: iirc we had a thread re this ; the gnarl is roughly similar to xilinx reversing ( they switch chip revisions erry quarter or so, by the time a card is ~acceptably reversed , it is long out of print )
(asciilifeform) asciilifeform: the problem w/ that kinda thing (aside from xilinx lockin re periphs , already mentioned) is this.
(asciilifeform) asciilifeform: punkman: in xilinx's vlsi, i.e. they encourage the use of xilinx-proprietary on-die periphs, if you want to port such design to e.g. ice40 or own silicon, nodice
(asciilifeform) asciilifeform: as for 'precursor', why thefuq would i buy a 500$ xilinx devboard. already sitting on a tall pile of same, of erry conceivable kind.
(asciilifeform) dulapbot: Logged on 2019-12-27 16:12:02 asciilifeform: amberglint: the huang fella is a вредитель , likely sponsored directly by the enemy. consider: with what it cost to bake his shitware to date, one could easily order a properly-open fpga made from 0. but instead he pushes xilinx's.
(asciilifeform) asciilifeform: punkman: i recall that box, an earlier variant was hyped during #ba days even. gotta love how author uses word 'open' with straight face to talk about a box which runs on a supersize xilinx, for instance.
(asciilifeform) asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2021-06-10#1038526 << ice40 has moar LUTs than any '80s fpga. and documented. i suspect you meant to ask '1980s FPGAs with the LUT count of high-end xilinx from 2021'
(asciilifeform) Aerthean: I've also done some development on the lower-level Zynq using Vivado, which also doesn't require a paid for license. Though I have access to a license at work for some of the bigger Xilinx FPGAs.
(asciilifeform) Aerthean: I'm going to be doing some development on one of the beefier Xilinx Spartan-6s that use ISE rather than Vivado
(asciilifeform) asciilifeform: iirc that one sat on a xilinx, and had sumthing like iron gc
(asciilifeform) snsabot: Logged on 2020-08-20 18:09:04 asciilifeform: Aerthean: xilinx's biz model requires the periodic breaking of compat.
(asciilifeform) asciilifeform: verisimilitude: many well-known historic chip vendors have been (and are to this day) fabless. e.g. sun, xilinx, nvidia, apple.
(asciilifeform) gregorynyssa: problem is, no one sells densely etched LUTs as a generic commodity. everyone (Xilinx, Intel...) sells "solutions," or worse, "experiences," but I still see two narrow avenues out of this mess:
(asciilifeform) asciilifeform: see the src, i specifically did not use ~any~ coad from xilinx's libs.
(asciilifeform) asciilifeform: xilinx is epic ball of yarn, entirely comparable to microshit's products
(asciilifeform) Aerthean: Eventually I gave up as I had other work to do, and didn't have the motivation to find and tear out all the Xilinx'isms that prevented it from building
(asciilifeform) Aerthean: Ah, yeah I followed along with some of the musl work, I put some effort into building a musl-based FreeRTOS system for a Xilinx Zynq
(asciilifeform) asciilifeform: ben_vulpes: e.g. FG's controller (albeit w/ evil turdware toolchain for linux, then, for xilinx) from mp's prodding to production in <8wks
(asciilifeform) asciilifeform: open ('opensores') toolchain, unlike xilinx's
(asciilifeform) asciilifeform: amberglint: the huang fella is a вредитель , likely sponsored directly by the enemy. consider: with what it cost to bake his shitware to date, one could easily order a properly-open fpga made from 0. but instead he pushes xilinx's.
(trilema) a111: Logged on 2019-04-17 22:45 asciilifeform: i suspect that proprietor of 'gowin' et al is not thinking 'how do i vanquish the reich' but instead 'how do i chisel enuff revenue away from xilinx to build palace in miami for my 4 sons'. and i betcha already built.
(trilema) asciilifeform: i suspect that proprietor of 'gowin' et al is not thinking 'how do i vanquish the reich' but instead 'how do i chisel enuff revenue away from xilinx to build palace in miami for my 4 sons'. and i betcha already built.
(trilema) a111: Logged on 2019-04-17 19:26 asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'
(trilema) asciilifeform: in principle it would be trivial to bake a standardized, commoditized fpga. the 'gowin' people could have easily done this, an' published the interconnect scheme and the delay map. BUT what no one knows how to do, is to make this a +ev proposition. observe, the chinese had no interest in trying to commoditize , but instead went 'we'll do exactly what xilinx does but slightly cheaper , out of chinesium'
(trilema) asciilifeform: but if you want deterministic paths, currently yer stuck using the vendor shitware. ( what's worse, even on ye olde xilinx apparently it is impossible to write e.g. a working 200MHz+ dram controller from 1st principles, yer forced to use the vendor's shitware that actually knows the gate delays, to equalize the paths )
(trilema) asciilifeform: xilinx incidentally has already confessed to resorting to 'cubism'/layered dies, to meet their claimed cell counts.
(trilema) asciilifeform: mp_en_viaje: y'mean the faux-asics that were relabeled xilinxen lol
(trilema) asciilifeform: not wholly unrelatedly, asciilifeform's semi-automated archaeology birthed a logworthy output recently. seems like in '80s there was an outfit, 'algotronix', that xilinx bought an' killed , to bury the product in patent liquishit. had entirely homogeneous fpga , made from identical ~200-transistor cells ( with simple north-south-east-west tile interconnects, and 1 flipflop inside, configged via 16bit shift register per cell, connecte
(trilema) asciilifeform: compare with the fg xilinx die , the latter has no fancy package, and is entirely homogeneous at 35kV.
(trilema) mircea_popescu: and the mechanism that'll work on intell will then work on xilinx, and so on.
(trilema) asciilifeform: if i wanted to continue using closed shitware, i'd be entirely happily fitting rsatron into my 400,000-LUT xilinx etc
(trilema) asciilifeform: ( e.g. classic FG , is only 'upgradeable' because xilinx doesn't offer an otp chip )
(trilema) mircea_popescu: not the same thing ~at all~ however. for one thing, it comes with the xilinx shitstack. for the other, it's a sack large enough to contain a car. we're talking about the actual car.
(trilema) asciilifeform: ( naturally it's the big-fpga monopolist, xilinx . but it's there. )
(trilema) asciilifeform: i've built, fwiw, for mips ( 32 an' 64 -wide ), for arm (ditto), even for 'microblaze' ( spoiler: not an actual iron, but xilinx's oddball 'demo cpu', exists nowhere else but 'virtex' demo boards, of which i have an embarrassingly tall pile ) -- but i ain't ever built for s390, or 68k ...
(trilema) asciilifeform: not even the $1k xilinx'en.
(trilema) asciilifeform: the other is political, all of the existing vendors obfuscate and keep seekrit the necessary docs to actually program the thing. ice40 happens to have been reversed, but it is ruinously small ( still ~150x bigger than the miniature xilinx i baked FG from, however , but too small even for 4096bit adder )
(trilema) asciilifeform: for that matter current FG is baked on fpga, from evil old xilinx.
(trilema) asciilifeform: doubtful, all of the examples i've been able to peek into, are full of xilinx.
(trilema) a111: Logged on 2018-06-14 18:51 asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with xilinx fpgas (in varying conditions of mutilation)
(trilema) asciilifeform: mircea_popescu: iirc we had a thread re this ; the gnarl is roughly similar to xilinx reversing ( they switch chip revisions erry quarter or so, by the time a card is ~acceptably reversed , it is long out of print )
(trilema) asciilifeform: i'd also like to be rid of xilinx sooner rather than later.
(trilema) asciilifeform: ice40, unlike the xilinx cplds, also includes 32kB of onboard sram. so possibly can have small cache, or extra registers, or some other useful item.
(trilema) asciilifeform: it eats 71 of the 72 logic cells in the old xilinx cpld.
(trilema) asciilifeform: trinque: in trips down lulzmemorylane, asciilifeform blew a good % of 2011 on halfcocked attempt to get miner going on surplus-usg boards with xilinx fpgas (in varying conditions of mutilation)
(trilema) asciilifeform: this one is something like a xilinx but with metal rom instead of the usual LUT rom.
(trilema) asciilifeform: xilinx datashit says it's an arm7
(trilema) mircea_popescu: now, it has a whole pile of "intel me" bs (did i mention - xilinx ?) but nevertheless
(trilema) asciilifeform: aa that -- that's what they stuffed into recent xilinxen in place of the old ppc core
(trilema) mircea_popescu: zynq-7000, a xilinx wrapper
(trilema) nonlinear: Oh, I hope an opensource flow for Xilinx is achieved.
(trilema) a111: Logged on 2018-01-11 16:49 apeloyee: http://btcbase.org/log/2018-01-04#1764242 << do I understand correctly that there's nowhere to store the result, as there seems to be enough hw adders in an 'ice'?also, it seems that the same authors are trying to reverse some xilinx nao: https://symbiflow.github.io/
(trilema) asciilifeform: mircea_popescu: re the xilinx reversing attempt , http://btcbase.org/log/2018-01-11#1769036 << prev thread
(trilema) asciilifeform: for an every-transistor-documented xilinx 'virtex' fpga clone ? would pay
(trilema) a111: Logged on 2018-01-11 16:58 a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
(trilema) asciilifeform: i still dislike having to use toolchain from hitler to compile the bitstream. and thereby the current fg is the last time i use a xilinx in a product.
(trilema) apeloyee: it's the 1 product currently sold, that's worth buying. << and the xilinx item in 'fuckgoats'?
(trilema) asciilifeform: apeloyee: they could in principle try intel-style fascism with built-in rsa sig verifier or the like. but afaik the only vendor to date to attempt any such thing, was xilinx, and it wasn't even in earnest
(trilema) asciilifeform: the smaller ones are 'sea of gates' as they are intended to be used for glue logic, and emphasize predictable path timing ( the analogous xilinx series is the 95xx , as used in FUCKGOATS )
(trilema) asciilifeform: apeloyee: the larger chips by lattice co are already xilinx-like
(trilema) a111: Logged on 2017-09-02 19:58 asciilifeform: large xilinx chips also have 'hard' periphs inside, e.g. multers, adders, shifters, various
(trilema) a111: Logged on 2017-09-02 20:02 asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
(trilema) a111: Logged on 2018-01-11 16:49 apeloyee: http://btcbase.org/log/2018-01-04#1764242 << do I understand correctly that there's nowhere to store the result, as there seems to be enough hw adders in an 'ice'?also, it seems that the same authors are trying to reverse some xilinx nao: https://symbiflow.github.io/
(trilema) asciilifeform: http://btcbase.org/log/2018-01-11#1769036 << this is correct, it simply doesn't have enough LUTs to store even the 2 operands, not even speaking of result. however xilinx is a dead end : because it is 1) nonhomogeneous 2) they switch the internals regularly, specifically to prevent a reversing from being useful in the long term. see old xilinx threads in the logs for detail
(trilema) apeloyee: http://btcbase.org/log/2018-01-04#1764242 << do I understand correctly that there's nowhere to store the result, as there seems to be enough hw adders in an 'ice'?also, it seems that the same authors are trying to reverse some xilinx nao: https://symbiflow.github.io/
(trilema) jhvh1: asciilifeform: Xilinx DS065 XC9572 In-system Programmable CPLD Data Sheet: <https://www.xilinx.com/support/documentation/data_sheets/ds065.pdf>; XC9572 -15PQG100C Xilinx Inc. | Integrated Circuits (ICs) | DigiKey: <https://www.digikey.com/product-detail/en/xilinx-inc/XC9572-15PQG100C/122-1445-ND/966626>; XC9572 -15PC44I Xilinx Inc. | Integrated Circuits (ICs) | DigiKey: (1 more message)
(trilema) asciilifeform: ( you wouldn't call an 'implementation' of e.g. ppc cpu that simply uses xilinx 'virtex' series' built-in ppc core, an implementation. apply same rule to pci.)
(trilema) asciilifeform: i specifically exclude devices like xilinx and altera series with ~built-in~ pcie -- these are not, properly speaking, fpga
(trilema) asciilifeform: ( after which xilinx & altera market will look like cisco's -- tame idjits only )
(trilema) asciilifeform: i had a xilinx board (shaped like pc mobo, with pci even ) that had this feature
(trilema) phf: right, that's the first thought when you have your cadr up. "oh wait, i need to go fuck around with xilinx tooling to make any kind of changes here)
(trilema) asciilifeform: lego toy got 'xilinxized' in early 2000s
(trilema) asciilifeform: re the archs -- lattice ice is analogous to children's toy 'lego' where you get 9,000 identical bricks; xilinx ( and altera, and the 'adult' lattice fpga on fancy dev boards ) are analogous to... i guess the 'erector' toy, where there are a certain number of fungible pieces, but also ~a~ motor, ~a~ heavy iron base, a quantity of gears, etc.
(trilema) asciilifeform: ( and are the reason why xilinx has not been satisfactorily reversed a la ice, and not likely to be before going out of print )
(trilema) asciilifeform: large xilinx chips also have 'hard' periphs inside, e.g. multers, adders, shifters, various
(trilema) asciilifeform: ( this is a rough measure, because not all LUTs are created equal, naturally, xilinx has somewhat different ones in the cpld series vs 'spartans', and lattice has yet different, and altera -- yet different, etc )
(trilema) asciilifeform: ( xilinx toolchain shits out this figure in the report )
(trilema) asciilifeform: phf: if you're content to test parker's cadr, your existing xilinx board oughta do the job
(trilema) a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
(trilema) asciilifeform: folx who are willing to use lattice's closed shitdevchain buy the larger parts, where the dev boards are comparable to xilinx.
(trilema) asciilifeform: but smaller than all but the smallest xilinx 'spartan' parts.
(trilema) asciilifeform: the problem is that it's xilinx.
(trilema) asciilifeform: you can get ANYTHING you want on a xilinx board, phf
(trilema) asciilifeform: phf: that looks like a xilinx
(trilema) asciilifeform: ( rather like xilinx, if you're a reformed xilinxist )
(trilema) asciilifeform: re fpga ( there were various 'i'ma throw something together, with 11 different closed dramcontroller, nic, etc from xilinx lib ) , a german, and i fughet who else, all similar
(trilema) asciilifeform: mircea_popescu: if you'd like to pen a 'can haz the pill against your $B 'intellektual property' racket for phreee? ' letter to lattice, go ahead. i did xilinx.
(trilema) a111: Logged on 2017-08-22 12:25 asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
(trilema) asciilifeform: but lattice per se is EXACTLY like xilinx, same profit model, closed arch, license 'ip cores'. their larger flagship fpga is exactly like xilinx 'spartan', full of proprietary peripherals, and that's the one that tends to get packaged into devboards with nic etc
(trilema) a111: Logged on 2017-08-21 21:30 spyked hates xilinx with passion. if only because of the bloated software
(trilema) asciilifeform: i will be phasing xilinx out of my product line entirely, also.
(trilema) asciilifeform: i last leeched the xilinx hog in 2011 and don't intend to ever update.
(trilema) spyked hates xilinx with passion. if only because of the bloated software
(trilema) asciilifeform: if you're used to working with, e.g., xilinx 'spartan' or 'virtex' series, it will feel VERY tight.
(trilema) spyked: hm. I'ma read about it. I only used xilinx FPGAs myself
(trilema) mircea_popescu: you know, originally tmsr embeddable work was done on xilinx. recently discovered superior alternative,
(trilema) asciilifeform: it's their ver of the xilinx virtex, full of proprietary special blox of various sorts
(trilema) asciilifeform: ( these are ubiquitous for xilinx & altera )
(trilema) asciilifeform: ( not a high bar, but probably enough to say now that next FUCKGOATS will NOT feature a xilinx no moar )
(trilema) asciilifeform: ( not even substantially slower than xilinx chain. though i have currently nfi re output quality in re path delays )
(trilema) asciilifeform: ( that doesn't rely on closed xilinx 20GB turdchain to fill, doesn't contain a flash rom, doesn't double as a frying pan )
(trilema) asciilifeform: the interesting bit is that linked d00dz stuffed it in 60% of cheap xilinx (lx9, i have a pile of'em)
(trilema) asciilifeform: xilinx + sdram + usb20tron inside.
(trilema) asciilifeform: summary of noose piece is 'xilinx+GBnic is nao cheap, who wants -- can get'
(trilema) asciilifeform: dun get quite so hot an' bothered, it's still made of traditional xilinx (which needs the massive toolchain) and still contains sdram ( for which no controller other than xilinx's , works ) but this board is actually useful -- in comparison with my existing aging 'ml501' ( as pictured in http://www.loper-os.org/?p=702 , http://www.loper-os.org/?p=797 )
(trilema) asciilifeform: to prototype xilinx+GB
(trilema) asciilifeform: they didn't break anything, it's still a stock xilinx chip
(trilema) mircea_popescu: asciilifeform basuically this crash-safe thing looks like a mostly theoretical xilinx blob
(trilema) a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (xilinx, altera, lattice, a few others) have the same business model
(trilema) a111: Logged on 2016-10-03 13:35 asciilifeform: mepian: http://btcbase.org/log/2016-10-03#1551507 << please read the xilinx threads .
(trilema) a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;
(trilema) asciilifeform: erlehmann: i manufacture and sell a product ( http://nosuchlabs.com/hardware.html ) with a xilinx cpld in it
(trilema) mircea_popescu: xilinx could work as cpu in theory!
(trilema) asciilifeform: mircea_popescu: next rev of board will have, for lulzies, a not-xilinx
(trilema) mircea_popescu: asciilifeform xilinx!
(trilema) mod6: <+asciilifeform> even build -- himself. << one of the things im gonna be doing here, maybe with some handholding, is flashing xilinx chip with your fg.v
(trilema) mod6: the chip i've got is a 'xilinx spartan XC3S500E'
(trilema) mod6: i did get that xilinx platform cable usb deal in the mail too.
(trilema) mod6: i was thinking about taking my xilinx board and seeing if I can throw your fg-genesis on there.
(trilema) mircea_popescu: it's examinable in the sense xilinx is examinable.
(trilema) mircea_popescu: i don't know how you can audit a xilinx chip. but if you did, asciilifeform would definitely be interested in hearing.
(trilema) mircea_popescu: well, we don't trust xilinx for critical infreastructure for the ~same reason we don'tr trust windows.
(trilema) mircea_popescu: so you are trusting xilinx to actually do what it says ? and this with code that you can't audit ?
(trilema) a111: Logged on 2017-03-28 15:03 mod6: i did wanna get a few xilinx boards to play with... but first ill see what I can learn with the other stuff I got. i also bought a soldering iron.
(trilema) asciilifeform: http://btcbase.org/log/2017-03-28#1633177 << i'll point out, FUCKGOATS even doubles as a (very small, actually 2nd smallest chip they sell) xilinx dev board...
(trilema) mod6: i did wanna get a few xilinx boards to play with... but first ill see what I can learn with the other stuff I got. i also bought a soldering iron.
(trilema) asciilifeform: gabriel_laddel_p: if you're thinking of nic-on-xilinx, every single one (with the exception of the 10BaseT half-duplex that's floated around since 1990s) relies on a xilinx-proprietary fabric turd
(trilema) asciilifeform: ye olde chip racket, as exemplified by xilinx (see thread), where 'by the time the docs leak, not only we stopped making it 15 years ago but go and buy even secondhand one!' -- remains operational.
(trilema) asciilifeform: it'd handily fit in a, e.g., xilinx spartan6.
(trilema) mircea_popescu: (lasts, not because chickens will become xilinx fans, but because the last people who know how it works will die, and then their writings will... BE MOVED TO NEW DIRECTORIES. and that's that.)
(trilema) asciilifeform: but when xilinx's synth tool stubbornly refused to map the collective reset in FUCKGOATS to the global reset pin, i found the answer with, yes, a few hours of google.
(trilema) asciilifeform: i will point out that, for all of the horror of the 100% closed and ~15 GB (yes) mass of the xilinx dev chain, it runs on ANY LINUX BOX
(trilema) mircea_popescu: xilinx.e-technik.uni-rostock.de___139.30.202.12/ << lol!
(trilema) asciilifeform: http://btcbase.org/log/2016-10-15#1555681 << a standard xilinx jtagtron should work
(trilema) a111: Logged on 2014-12-11 01:52 asciilifeform: decimation: notice that all known fpga manufacturers (xilinx, altera, lattice, a few others) have the same business model
(trilema) a111: Logged on 2015-06-17 13:17 asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;
(trilema) asciilifeform: mepian: http://btcbase.org/log/2016-10-03#1551507 << please read the xilinx threads .
(trilema) mod6: im gonna get me one of these xilinx boards.
(trilema) asciilifeform: i was able to make 10baseT ethernet meet timing spec without using xilinxisms
(trilema) mircea_popescu: well it's unclear what the fuck it'll be, but it's pretty evident, at least to me, that the chinese ARE trying to erode the whole xilinx tower of ip.
(trilema) asciilifeform: and if it were, they are happy to clone xilinx and ship pirate copy of the binary turdchain with it.
(trilema) mircea_popescu: sure. but xilinx competition is first step.
(trilema) asciilifeform: ever see manual for, e.g., xilinx fpga? it is simply a mass of these turds.
(trilema) pete_dushenski: o hey xilinx has market cap of $12 bn aka 1/30th of facebook.
(trilema) asciilifeform: pete_dushenski: xilinx and altera make $B+ of them / yr and they aren't going into tv sets etc.
(trilema) ascii_deadfiber: if i could be arsed i'd compile it in my xilinx toolchain and see what max clock is
(trilema) asciilifeform: (re: 1 - e.g., reversed xilinx 4000 series, is ~useless~, as you cannot buy it in any kind of qty)
(trilema) sbp: "and only xilinx's closed turd knows where they are in the routing fabric" — ugh
(trilema) asciilifeform: (inside is also a xilinx fpga and some sram.)
(trilema) asciilifeform: and in the 'roadmap' link we specifically see 'xilinx.'
(trilema) asciilifeform: gabriel_laddel: fpga is pretty much never mounted in a socket (the low end xilinx cpld, e.g., 95xx series, do come in plcc - but high pin count makes this a bitch)
(trilema) asciilifeform: today reversing a xilinx chip is largely a waste of time, a good chunk of the functionality is in quite un-fpgaish special-purpose chunks which get reshuffled with each new model
(trilema) asciilifeform: http://log.bitcoin-assets.com/?date=01-12-2015#1334537 << famous among aficionados. 'neocad' actually reversed the time's xilinx fpga line. 'had to die.'
(trilema) gabriel_laddel: To any "hackers" reading the logs - rather than going after hackteam, try xilinx, lattice semiconductor next time?
(trilema) ascii_field: this all happened before, with xilinx
(trilema) asciilifeform discovered, during unrelated research, that xilinx's 'coolrunner' cpld series - a very simple programmable logic gizmo with very homogeneous/regular physical structure - can hold a simple risc cpu...
(trilema) assbot: azonenberg:xilinx:xc2c32a [Silicon Pr0n] ... ( http://bit.ly/1HdkxI1 )
(trilema) ascii_field: ^ of interest to all 'xilinx' aficionados
(trilema) ascii_field: and you don't have the ones you might like, but solely the ones the chip came with from xilinx etc
(trilema) ascii_field: (and only a paid-up, to the tune of 100K+ usd, or well-cracked, xilinx toolchain, will even talk to the $200-300 ones)
(trilema) ascii_field: price some of the larger xilinx chips
(trilema) assbot: Logged on 17-06-2015 17:32:11; ascii_field: (xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
(trilema) ascii_field: (xilinx, altera, actel, etc. ~all~ make the bulk of their revenue by charging rent for 'properties' like 'the right to have a network card' in your fpga)
(trilema) assbot: Logged on 17-06-2015 13:17:59; asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;
(trilema) asciilifeform: the entire thing is cynically deliberate. notice how, e.g., xilinx boards, come with ethernet jack and magnetics? well, you can't actually ~use~ the ethernet without paying a per-unit license fee to the bastards
(trilema) asciilifeform: you can pick up a textbook and write a dram controller for fpga from first principles - and it won't work. because, for starters, only a small number of output cells in the chip can function on both rising and falling edge of clock cycle (what 'ddr' means) and only xilinx's closed turd knows where they are in the routing fabric;
(trilema) asciilifeform: http://log.bitcoin-assets.com/?date=17-06-2015#1165915 << key detail: 'IP-Core : MIG V:3.6.1'. that's 'memory interface generator', xilinx's gui turd. it shits out code which is a mere wrapper on a closed-source gigantic steaming pile of shit. and the output is unique to a particular model and subtype of chip.
(trilema) asciilifeform: mention of xilinx is especially on the point because a bit-flip in fpga routing fabric is catastrophic
(trilema) asciilifeform: i also have boxes that run closedsource linux crapolade (e.g., xilinx toolchain)
(trilema) asciilifeform: it had a xilinx spartan 1st ed. fpga inside. and was built like a tank.
(trilema) ascii_field: (before anyone spits back the old paper re: the fact of c-gates implemented on xilinx fabric - go and see how many of them you can fit. and how much room left for interconnects.)
(trilema) ascii_field: gabriel_laddel: to avoid rehashing ancient thread for a fifth time, stuck at the realization that reversing xilinx is futile.
(trilema) ascii_field: at one time there was much crowing re: a 'xilinx fpga backdoor'
(trilema) ascii_field: mats: neato, there was a similar project for xilinx 'virtex'
(trilema) ascii_field: trinque: you're talking about reverse-engineering, a la nvidia driver, xilinx (see old thread, etc.)
(trilema) asciilifeform: it's a little thing with a 'xilinx' fpga (nonvolatile) and 'ftdi' usb2 diddler
(trilema) mircea_popescu: asciilifeform: at the risk of repeating the last 100+ xilinx threads <<< basically, there was no torvalds for hardware. yet.
(trilema) mircea_popescu: asciilifeform: xilinx ships a set of identially-functioning turdlibraries for both languages. << one wonders how they actually achieved this.
(trilema) BingoBoingo: Sure, but what sphicter sculpts the Xilinx turd.
(trilema) asciilifeform: closes xilinx turd, yes
(trilema) asciilifeform: at the risk of repeating the last 100+ xilinx threads - the closed architecture of -all- fpga vendors is specifically to enable this 'business model'
(trilema) asciilifeform: xilinx ships a set of identially-functioning turdlibraries for both languages.
(trilema) asciilifeform wrote a ddr2 controller for 'xilinx' chip once. it is amazingly easy to create a dysfunctional one with behaves like, for instance, the one pictured in that paper.
(trilema) asciilifeform: almost as much as the first (and last, and only) xilinx part that had open docs from the vendor
(trilema) asciilifeform: decimation: notice that all known fpga manufacturers (xilinx, altera, lattice, a few others) have the same business model
(trilema) asciilifeform: a forcibly blown open 'xilinx' soft/hard stack would be a good start though.
(trilema) decimation: my understanding is tha altera is generally easier to deal with here, because they actually do their own r&d to produce these 'ip cores', whereas xilinx tends to contract it out - involving third parties in your product
(trilema) asciilifeform: e.g., xilinx wants you to prototype on their fpga, and then offers massively-discounted asic process which simply consists of their fpga die plus custom metallization layer.
(trilema) mircea_popescu: <asciilifeform> you'd have to buy 'xilinx' or 'altera' - the company - to go with the chip. and publicly gut it. << it will happen.
(trilema) assbot: debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL | Comp.Arch.FPGA | FPGARelated.com
(trilema) asciilifeform: you'd have to buy 'xilinx' or 'altera' - the company - to go with the chip. and publicly gut it.
(trilema) asciilifeform: (each new series of 'xilinx' chip has considerably altered internals, to make past reverser's efforts less useful)
(trilema) asciilifeform: decimation: both 'xilinx' and 'altera' make the bulk of their profit by renting out the right to use 'cores' (as they call them) - libraries, to a normal person
(trilema) asciilifeform: because 'xilinx' sells, by the tonne, a large fpga with built in 'ppc' cores.
(trilema) mircea_popescu: <asciilifeform> bounce: search channel logs re: at least three separate discussions of how this came to be << you know, giving terms like "xilinx" is better than an empty search entreaty. he doesn't know what to search for.
(trilema) assbot: NSA Approved Defense-Grade Spartan-6Q FPGA in Production for Highest Level Cryptographic Capabilities Strengthens Xilinx Secure Leadership - Aug 31, 2011
(trilema) asciilifeform: 'xilinx' in particular brags of 'nsa certified' whatevers.
(trilema) asciilifeform: the vendors (there are exactly two worth mentioning, 'xilinx' and 'altera' - the others sell miniscule turdlets, most often with zero linux toolchain support) also play fast & loose with the word 'gate'
(trilema) decimation: yeah the old xilinx part
(trilema) decimation: the xilinx board?
(trilema) asciilifeform: decimation: xilinx and altera both make tightly 'closed' chips, for reasons discussed in agonizing detail earlier
(trilema) RagnarDanneskjol: on the strreet, yes, but any industrial embedded stuff is still xilinx
(trilema) asciilifeform: BingoBoingo: if it's a 'xilinx' or 'altera' - you're stuck with the vendor's closed turd.
(trilema) asciilifeform: (actually there may be. fpga/cpu combo is a dime a dozen - xilinx made ppc/fpga cores for ages. but a modern pc arch cpu is something rather else)
(trilema) asciilifeform: but at least these were traditional fpga and one could (at least in the case of xilinx) use linux toolchain, traditional vhdl/verilog, etc
(trilema) pankkake: Our first larger scale immersion cooled cluster consisted of 6048 Xilinx®Spartan-6 FPGAs in 24 tanks and was built in early 2012 with the Bitcoin still below $5.
(trilema) asciilifeform: it was also the only xilinx chip with 100% documented internals.
(trilema) asciilifeform: it does not automatically follow that one should not buy xilinx
(trilema) asciilifeform: incidentally, xilinx might as well be run out of ft. meade
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