Results 1 ... 29 found in all logged channels for 'propagation delay'
(pest) jonsykkel[asciilifeform]: # of pakets sent can be reduced somwat by adding a propagation delay before relaying. only relay to ppl u didnt yet recv a copy from. such mechanism alredy exists in specful pestron in form of hearsay buffer. maybe can be generalized for all pakets that are to be flod routed
(pest) asciilifeform in experiments w/ udp, not found any instances of macroscopic propagation delay ( i.e. moar than one'd expect from 'ping time' ) from anywhere to anywhere
(asciilifeform) dulapbot: Logged on 2022-03-29 09:12:44 asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2022-03-29#1090185 << obv. can connect >1, but they won't 'behave like larger array', given propagation delays and sparseness of i/o
(asciilifeform) asciilifeform: http://logs.nosuchlabs.com/log/asciilifeform/2022-03-29#1090185 << obv. can connect >1, but they won't 'behave like larger array', given propagation delays and sparseness of i/o
(asciilifeform) asciilifeform: verisimilitude: cellular structure solves all kinds of idiocies from conventional comp design, yes.
(trilema) bvt: i get the propagation delay physics; i guess the question is how much is lost due to suboptimal design tools, vs max capability of hardware
(trilema) asciilifeform: this is why fpga design ~never runs at anywhere near the max switching rate specced by the device vendor. a good synth tool 1) tries to minimize the delays 2) gives you an accurate figure for max clock, and for propagations of individual paths ( if you have e.g. dram hanging off the thing, these are critical )
(trilema) asciilifeform: ^ astro puzzle : calculate the minimal propagation delay in this 'fpga'. ( just how close can one park a jupiter to another before they merge.. etc )
(trilema) asciilifeform: if make smaller than 4, seems to be (empirically) losing idea, the propagation delays from many small cells eat you alive
(trilema) asciilifeform: i would've added row/column lines , to cut down propagation delay when you bake internal bus, but it's moar or less exactly The Right Thing as-is
(trilema) asciilifeform: d in series. ) simple enuff to simulate deterministically (and calculate propagation delays on paper..)
(trilema) asciilifeform: cuz, elementarily, it would have to contain coupla 10k actual transistors inside, and impose their propagation delay on the output.
(trilema) asciilifeform: asciilifeform's fg test process for freshly-received boards, for instance, included an (unpublished, and won't be published any time soon) set of test circuits for the fpga , that characterized the propagation delays.
(trilema) asciilifeform: mp_en_viaje: the q is not whether a human reverser can find nic stack with his eyes, but whether you can stuff a robotic 'finder-diddler' of same into general-purpose sea of gates fabric , and still have item that passes inspection (incl. having the expected homogeneous propagation delays b/w the gates)
(trilema) asciilifeform: OriansJ: incidentally, a pattern matcher on i/o pin will affect propagation delay
(trilema) asciilifeform: the ice40 tops out at 250MHz (and drops rapidly when you fill it up, from switch fabric propagation delay)
(trilema) a111: Logged on 2017-07-12 00:56 asciilifeform: mod6 et al : in other noose, i have a working experimental build with No_Implicit_Conditionals, No_Implicit_Heap_Allocations, No_Implicit_Dynamic_Code, No_Secondary_Stack, No_Exception_Propagation, No_Tasking, No_Protected_Types, No_Delay, No_Allocators, No_Dispatch restrictions.
(trilema) asciilifeform: mod6 et al : in other noose, i have a working experimental build with No_Implicit_Conditionals, No_Implicit_Heap_Allocations, No_Implicit_Dynamic_Code, No_Secondary_Stack, No_Exception_Propagation, No_Tasking, No_Protected_Types, No_Delay, No_Allocators, No_Dispatch restrictions.
(trilema) asciilifeform: thing is, you get the clock rate of fpga. and same energy consumption. (~same propagation delays).
(trilema) asciilifeform: http://log.bitcoin-assets.com/?date=06-02-2016#1397765 << if you crunch the simple arithmetic re: propagation delays, it reveals that one of two things: a) whole thing is a scam, not actually intended to happen in physical reality b) collectivized, 'kolhoz' of gaming processor will be installed on street corner router cabinets, one per 100 houses or so, this will go great with ownership of actual computer being Officially forb
(trilema) asciilifeform: on top of this, all of the critical paths in the circuit must have approximately same propagation delay - or the thing ~won't work at all~
(trilema) asciilifeform: if one were to read the data sheet (scan, http://www.155la3.ru/datafiles/2lb402_tu_1975.pdf ) will find that it had around 50-60 nSec propagation delay. which is pretty good for the period
(trilema) asciilifeform: welcome to propagation delays 100s of mSec long. and idiot proprietary toolchains
(trilema) asciilifeform: because it uses the general-purpose routing fabric, and propagation delays eat you alive.
(trilema) decimation: asciilifeform: yeah I forgot about ECL. The point is, discrete logic need not be slow. However, at high speeds propagation delay is going to be a serious issue, which implies distributed clockless dataflow design.